ASIC/FPGA调试中的重复劳动与技能提升需求
问题概述
综合帖子与评论，硬件工程师在ASIC/FPGA调试中需花费数小时至数天盯视波形和指令痕迹，且缺乏系统化的问题解决技能提升方法。用户表达了对冗余劳动的厌倦，以及通过AI或结构化训练改进的渴望。
痛点标签
- 在ASIC/FPGA调试中需花费数小时至数天盯视波形和指令痕迹
- 缺乏系统化的方法来提升此类谜题式问题的解决技能，仅靠‘钻研’效率有限
待验证问题
- 是否存在能自动化波形/痕迹分析的工具能显著减少人工盯图时间？
- 是否有结构化的技能训练体系能帮助用户从‘钻研谜题’转向‘系统化问题求解’？
证据
原话 · @匿名
AI is really good at debugging failing tests so I no longer have to spend hours - sometimes it was even days - staring at waves and instruction traces. Tbh that's one thing I won't miss.
原话 · @匿名
Every time I see a Jane Street puzzle of this like I wonder in which way you can improve your problem solving skills for these things and how to extrapolate patterns from other things. I have a gut feeling that this is not only just grinding puzzles, there has to be a way to improve this. Curious if people have some insights on this
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